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Overview. Overview; Overview. The Application Centric Infrastructure (ACI) Fabric hardware includes an Application Policy Infrastructure Controller (APIC) appliance (a cluster of three controllers), one or more leaf switches, and one or more spine switches for each leaf switch (for switch compatibility, please see the Cisco Nexus 9000 Series Switches data sheets). In computing, a programmable interrupt controller (PIC) is an integrated circuit that helps a microprocessor (or CPU) handle interrupt requests (IRQ) coming from multiple different sources (like external I/O devices) which may occur simultaneously. It helps prioritize IRQs so that the CPU switches execution to the most appropriate interrupt handler (ISR) after the PIC assesses the IRQ's local APIC is not a piece of hardware shared by multiple logical processors, each logical processor has its own local APIC. Constrast that with physical memory, which is shared by multiple processors. Take a look at the basic diagram in chapter 2 of volume 1 of the software developer's manual, fig 2-6 and 2-7, for example. Intel® 400 Series Chipset On-Package Platform Controller Hub Online Register Database. Download as PDF. ID 615146. Date 08/09/2019. Version 1.2. Document Table of Contents. Introduction 8254 Timer Advanced Programmable Interrupt Controller (APIC) APIC Indirect CNVi PCI Configuration DCI PCR EMMC Additional EMMC Memory Mapped EMMC PCI LKML Archive on lore.kernel.org help / color / mirror / Atom feed * x2apic_wrmsr_fence vs. Intel manual @ 2020-03-02 16:11 Jan Kiszka 2020-03-02 16:20 ` Thomas Gleixner 2020-03-04 18:27 ` Dave Hansen 0 siblings, 2 replies; 6+ messages in thread From: Jan Kiszka @ 2020-03-02 16:11 UTC (permalink / raw) To: x86; +Cc: Linux Kernel Mailing List Hi all, as I generated a nice bug around fence vs Intel 253668-032US 10.5 EXTENDED XAPIC (X2APIC), , , , Manuals Brands Computer Equipment Webcam Intel Computer Equipment Webcam Intel 253668-032US 10.5 EXTENDED XAPIC (X2APIC), , , , 1 806 Download 806 pages, 5.71 Mb < > 10-16 Vol. 3 ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) 10.5 EXTENDED XAPIC (X2APIC) Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs. These thresholds have the capability of generating interrupts using the processor IA core's local APIC. Refer to the Intel 64 Architectures Software Developer's Manual for specific register and programming details. I don't find any descriptions about the sequence of disable IO-APIC and Local APIC in "Intel 64 and IA-32 Architectures software developer's manual volume 3A". Only erratum AVR31 for "Intel Atom Processor C2000 Product Family Specification Update". AVR31. Interrupts That Target an APIC That is Being Disabled May Result in a System Hang More efficient MSR interface to access APIC registers: To enhance inter-processor and self-directed interrupt delivery as well as the ability to virtualize the local APIC, the APIC register set can be accessed only through MSR-based interfaces in x2APIC mode. The Memory Mapped IO (MMIO) interface used by xAPIC is not supported in x2APIC mode. BIOS and Kernel Developer's Guide (BKDG) for AMD Family 16h Models 30h-3Fh Processors. Software Optimization Guide for AMD Family 16h Processors. Downloads a zip file, which includes a spreadsheet of instruction latencies. Revision Guide for AMD Family 16h Models 00h-0Fh Processors. Revision Guide for AMD Family 16h Models 30h-3Fh Processors. The Intel I/O Advanced Programmable Interrupt Controller is used to distribute external interrupts in a more advanced manner than that of the standard 8259 PIC. With the I/O APIC, interrupts can be distributed to physical or logical (clusters of) processors and can be prioritized. Each I/O APIC typically handles 24 external interrupts. Contents

275, 272, 980, 822, 362.